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NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_EMC_17

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Interpret as SW_MUX_CTL_PAD_GPIO_EMC_17

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: semc

2 (ALT2): Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs

3 (ALT3): Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: SRC_BOOT_MODE01 of instance: src
SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_EMC_17

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data